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| december 2010 doc id 15181 rev 4 1/44 44 l7980 2 a step-down switching regulator features 2 a dc output current 4.5 v to 28 v input voltage output voltage adjustable from 0.6 v 250 khz switching frequency, programmable up to 1 mhz internal soft-start and enable low dropout op eration: 100% duty cycle voltage feed-forward zero load current operation overcurrent and thermal protection vfqfpn3x3-8l and hsop8 package applications consumer: stb, dvd, dvd recorder, car audio, lcd tv and monitors industrial: pld, pla, fpga, chargers networking: xdsl, modems, dc-dc modules computer: optical storage, hard disk drive, printers, audio/graphic cards led driving description the l7980 is a step down switching regulator with 2.5 a (minimum) current limited embedded power mosfet, so it is able to deliver up to 2 a current to the load depending on the application conditions. the input voltage can range from 4.5 v to 28 v, while the output voltage can be set starting from 0.6 v to v in . requiring a minimum set of external components, the device includes an internal 250 khz switching frequency oscillator that can be externally adjusted up to 1 mhz. the qfn and the hsop packages with exposed pad allow reducing the r thja down to 60 c/w and 40 c/w respectively. figure 1. application circuit hsop8 exposed pad vfqfpn8 3x3 www.st.com
contents l7980 2/44 doc id 15181 rev 4 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4.1 type iii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.2 type ii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.6 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 l7980 contents doc id 15181 rev 4 3/44 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 pin settings l7980 4/44 doc id 15181 rev 4 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description out synch en comp v cc gnd fsw fb out synch comp v cc gnd fsw fb out synch en comp v cc gnd fsw fb out synch comp v cc gnd fsw fb table 1. pin description n. type description 1 out regulator output 2 synch master/slave synchronization. when it is left floating, a signal with a phase shift of half a period respect to the power turn on is present at the pin. when connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift. connecting together the synch pin of two devices, the one with higher frequency works as master and the other one as slave; so the two powers turn on have a phase shift of half a period. 3en a logical signal (active high) enable the device. with en higher than 1.2 v the device is on and with en is lower than 0.3v the device is off. 4 comp error amplifier output to be used for loop frequency compensation 5fb feedback input. connecting the output voltage directly to this pin the output voltage is regulated at 0.6v. to have higher regulated voltages an external resistor divider is required from vout to fb pin. 6f sw the switching frequency can be increased connecting an external resistor from fsw pin and ground. if this pin is left floating the device works at its free-running frequency of 250khz. 7 gnd ground 8v cc unregulated dc input voltage l7980 maximum ratings doc id 15181 rev 4 5/44 2 maximum ratings 3 thermal data table 2. absolute maximum ratings symbol parameter value unit vcc input voltage 30 v out output dc voltage -0.3 to v cc f sw , comp, synch analog pin -0.3 to 4 en enable pin -0.3 to v cc fb feedback voltage -0.3 to 1.5 p tot power dissipation at t a < 60c vfqfpn 1.5. w hsop 2 t j junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction-ambient (1) 1. package mounted on demonstration board. vfqfpn 60 c/w hsop 40 electrical characteristics l7980 6/44 doc id 15181 rev 4 4 electrical characteristics t j =25 c, v cc =12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition values unit min typ max v cc operating input voltage range (1) 4.5 28 v v ccon turn on v cc threshold (1) 4.4 v cchys v cc uvlo hysteresis (1) 0.12 0.35 r dson mosfet on resistance 160 180 m (1) 160 250 i lim maximum limiting current 2.5 3.0 3.5 a oscillator f sw switching frequency 225 250 275 khz (1) 220 275 v fsw fsw pin voltage 1.254 v d duty cycle 0 100 % f adj adjustable switching frequency r fsw =33k 1000 khz dynamic characteristics v fb feedback voltage 4.5v functional description l7980 8/44 doc id 15181 rev 4 5 functional description the l7980 is based on a ?voltage mode?, constant frequency control. the output voltage v out is sensed by the feedback pin (fb) compared to an internal reference (0.6 v) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch. the main internal blocks are shown in the block diagram in figure 3 . they are: a fully integrated oscillator that provides sa wtooth to modulate t he duty cycle and the synchronization signal. its switching frequency can be adjusted by an external resistor. the voltage and frequency feed forward are implemented. the soft start circuitry to limit inrush current during the start up phase. the voltage mode error amplifier the pulse width modulator and the relative logic circuitry necessary to drive the internal power switch. the high-side driver for embedded p-channel power mosfet switch. the peak current limit sensing block, to handle over load and short circuit conditions. a voltage regulator and internal reference. it supplies internal circuitry and provides a fixed internal reference. a voltage monitor circuitry (uvlo) that checks the input and internal voltages. a thermal shutdown block, to prevent thermal run away. figure 3. block diagram peak current limit oscillator s r q thermal shutdown soft- start en trimming uvlo 0.6v regulator & bandgap 1.254v 3.3v synch & phase shift en fb comp fsw gnd synch out vcc driver e/a pwm peak current limit oscillator s r q thermal shutdown soft- start en trimming uvlo uvlo 0.6v regulator & bandgap regulator & bandgap 1.254v 3.3v synch & phase shift en fb comp fsw gnd synch out vcc driver e/a pwm l7980 functional description doc id 15181 rev 4 9/44 5.1 oscillator and synchronization figure 4 shows the block diagram of the oscillator ci rcuit. the internal oscillator provides a constant frequency clock. its frequency depends on the resistor externally connect to fsw pin. in case the fsw pin is left floating the frequency is 250 khz; it can be increased as shown in figure 6 by external resistor connected to ground. to improve the line transient performance, keeping the pwm gain constant versus the input voltage, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see figure 5 .a). the slope of the sawtooth also changes if the oscillator fr equency is increased by the external resistor. in this way a frequency feed forward is implemented ( figure 5 .b) in order to keep the pwm gain constant versus the switching frequency (see section 6.4 for pwm gain expression). on the synch pin the synchronization signal is generated. this signal has a phase shift of 180 with respect to the clock. this delay is useful when two devices are synchronized connecting the synch pin together. when synch pins are connected, the device with higher oscillator frequency works as master, so the slave device switc hes at the frequency of the master but with a delay of half a period. this minimizes the rms current flowing through the input capacitor [see l5988d data sheet]. figure 4. oscillator circuit block diagram the device can be synchronized to work at higher frequency feeding an external clock signal. the synchronization changes the sawtooth amplitude, changing the pwm gain ( figure 5 .c). this changing has to be taken into a ccount when the loop stability is studied. to minimize the change of the pwm gain, the free running frequency should be set (with a resistor on fsw pin) only slightly lower than the external clock frequency. this pre-adjusting of the frequency will change the sa wtooth slope in order to get negligible the truncation of sawtooth, due to the external synchronization. clock generator ramp generator fsw sawtooth clock synchronization synch clock generator ramp generator fsw sawtooth clock clock synchronization synch functional description l7980 10/44 doc id 15181 rev 4 figure 5. sawtooth: voltage and frequency feed forward; external synchronization figure 6. oscillator frequency versus fsw pin resistor l7980 functional description doc id 15181 rev 4 11/44 5.2 soft-start the soft-start is essential to assure correct and safe start up of the step-down converter. it avoids inrush current surge and makes the output voltage increases monothonically. the soft -start is performed by a staircase ramp on the non-inverting input (v ref ) of the error amplifier. so the output voltage slew rate is: equation 1 where sr vref is the slew rate of the non-inverting input, while r1and r2 is the resistor divider to regulate the output voltage (see figure 7 ). the soft-start stair case consists of 64 steps of 9.5 mv each one, from 0 v to 0.6 v. the time base of one step is of 32 clock cycles. so the soft start time and then the output voltage slew rate depend on the switching frequency. figure 7. soft start scheme soft start time results: equation 2 for example with a switching frequency of 250 khz the ss time is 8 ms. 5.3 error amplifier and compensation the error amplifier (e/a) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. its non-invert ing input is internally connected to a 0.6 v voltage reference, while its inverting input (fb) and output (comp) are externally available for feedback and frequency compensation. in this device the error amplifier is a voltage mode operational amplifier so with high dc gain and low output impedance. the uncompensated error amplifier characteristics are the following: sr out sr vref 1 r1 r2 ------- - + ?? ?? ? = ss time 32 64 ? fsw ----------------- = functional description l7980 12/44 doc id 15181 rev 4 in continuos conduction mode (ccm), the transfer function of the power section has two poles due to the lc filter and one zero due to the esr of the output capacitor. different kinds of compensation networks can be used depending on the esr value of the output capacitor. in case the zero introduced by the output capacitor helps to compensate the double pole of the lc filter a type ii compensation network can be used. otherwise, a type iii compensation network has to be used (see chapter 6.4 for details about the compensation network selection). anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin. table 5. uncompensated error amplifier characteristics low frequency gain 100db gbwp 4.5mhz slew rate 7v/ s output voltage swing 0 to 3.3v maximum source/sink current 17ma/25ma l7980 functional description doc id 15181 rev 4 13/44 5.4 overcurrent protection the l7980 implements the overcurrent protection sensing current flowing through the power mosfet. due to the noise created by the switching activity of the power mosfet, the current sensing is disabled during the initial phase of the conduction time. this avoids an erroneous detection of a fault condition. this interval is generally known as ?masking time? or ?blanking time?. the masking time is about 200 ns. when the overcurrent is detected, two different behaviors are possible depending on the operating condition. 1. output voltage in regulation . when the overcurrent is sensed, the power mosfet is switched off and the internal reference (v ref ), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft start time (t ss , 2048 clock cycles). after this time, a new soft start phase takes place and the internal reference begins ramping (see figure 8 .a). 2. soft start phase . if the overcurrent limit is reached the power mosfet is turned off implementing the pulse by pulse overcurrent protection. during the soft start phase, under overcurrent condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. if at the end of the ?masking time? the current is higher than the overcurrent threshold, the power mosfet is turned off and it will skip one pulse. if, at the next switching on at the end of the ?masking time? the current is still higher than the threshol d, the device will skip two pulses. this mechanism is repeated and the device can skip up to seven pulses. while, if at the end of the ?masking time? the current is lower than the overcurrent threshold, the number of skipped cycles is decreased of one unit. at the end of soft start phase the output voltage is in regulation and if the overcurrent persists the behavior explained above takes place. (see figure 8 .b) so the overcurrent protection can be summarized as an ?hiccup? intervention when the output is in regulation and a constant current during the soft start phase. if the output is shorted to ground when the output voltage is on regulation, the overcurrent is triggered and the device starts cycling with a period of 2048 clock cycles between ?hiccup? (power mosfet off and no current to the load) and ?constant current? with very short on-time and with reduced switching frequency (up to one eighth of normal switching frequency). see figure 32. for short circuit behavior. functional description l7980 14/44 doc id 15181 rev 4 figure 8. overcurrent protection strategy 5.5 enable function the enable feature allows to put in stand-by mode the device.with en pin lower than 0.3v the device is disabled and the power consumptio n is reduced to less than 30 a. with en pin lower than 1.2 v, the device is enabled. if the en pin is left floating, an internal pull down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v cc compatible. 5.6 hysteretic thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150c. once the junction temperature goes back to about 130c, the device restarts in normal operation. the sensing element is very close to the pdmos area, so ensuring an accurate and fast temperature detection. l7980 application informations doc id 15181 rev 4 15/44 6 application informations 6.1 input capacitor selection the capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum rms input current required by the device. the input capacitor is subject to a pulsed current, the rms value of which is dissipated over its esr, affecting the overall system efficiency. so the input capacitor must have a rms current rating higher than the maximum rms input current and an esr value compliant with the expected efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 3 where io is the maximum dc output current, d is the duty cycle, is the efficiency. considering =1 , this function has a maximum at d=0.5 and it is equal to io/2. in a specific application the range of possible duty cycles has to be considered in order to find out the maximum rms input current. the maximum and minimum duty cycles can be calculated as: equation 4 and equation 5 where v f is the forward voltage on the freewheeling diode and v sw is voltage drop across the internal pdmos. the peak to peak voltage across the input capacito r can be calculated as: equation 6 where esr is the equivalent series resistance of the capacitor. i rms i o d 2d 2 ? -------------- - ? d 2 2 ------ - + ? = d max v out v f + v inmin v sw ? ------------------------------------ - = d min v out v f + v inmax v sw ? -------------------------------------- = v pp i o c in f sw ? ------------------------- 1 d --- - ? ?? ?? d d --- - 1d ? () ? + ? esr i o ? + ? = application informations l7980 16/44 doc id 15181 rev 4 given the physical dimension, ceramic capacitors can meet well the requirements of the input filter sustaining an higher input rms curren t than electrolytic / tantalum types. in this case the equation of c in as a function of the target v pp can be written as follows: equation 7 neglecting the small esr of ceramic capacitors. considering =1, this function has its maximum in d=0.5, thus, given the maximum peak to peak input voltage (v pp_max ), the minimum input capacitor (c in_min ) value is: equation 8 typically c in is dimensioned to keep the maximum peak-peak voltage in the order of 1% of v inmax in table 6. some multi layer ceramic capacitors su itable for this device are reported a ceramic bypass capacitor, as close to the vcc and gnd pins as possible, so that additional parasitic esr and esl are minimized, is suggested in order to prevent instability on the output voltage due to noise. the value of the bypass capacitor can go from 100 nf to 1 f. 6.2 inductor selection the inductance value fixes the current ripple flowing through the output capacitor. so the minimum inductance value in order to have the expected current ripple has to be selected. the rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. in the continuos current mode (ccm), the inductance value can be calculated by the following equation: table 6. input mlcc capacitors manufacture series cap value ( f) rated voltage (v) ta i y o yu d e n umk325bj106mm-t 10 50 gmk325bj106mn-t 10 35 murata grm32er71h475k 4.7 50 c in i o v pp f sw ? -------------------------- - 1 d --- - ? ?? ?? d d --- - 1d ? () ? + ? ? = c in_min i o 2v pp_max f sw ?? ----------------------------------------------- - = l7980 application informations doc id 15181 rev 4 17/44 equation 9 where t on is the conduction time of the internal high side switch and t off is the conduction time of the external diode (in ccm, f sw =1/(t on + t off )). the maximum current ripple, at fixed vout, is obtained at maximum t off that is at minimum duty cycle (see previous section to calculate minimum duty). so fixing i l =20% to 30% of the maximum output current, the minimum inductance value can be calculated: equation 10 where f sw is the switching frequency, 1/(t on + t off ). for example for v out =5 v, v in =24 v, i o =2 a and f sw =250 khz the minimum inductance value to have i l =30% of i o is about 28 h. the peak current through the inductor is given by: equation 11 so if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. the higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. in the table below some inductor part numbers are listed. table 7. inductors manufacturer series inductor value ( h) saturation current (a) coilcraft mss1038 3.8 to 10 3.9 to 6.5 mss1048 12 to 22 3.84 to 5.34 mss1060 22 to 47 5 to 6.8 wurth pd type l 8.2 to 15 3.75 to 6.25 pd type m 2.2 to 4.7 4 to 6 pd4 type x 22 to 47 2.6 to 3.5 sumida cdrh6d226/hp 1.5 to 3.3 3.6 to 5.2 cdr10d48mn 6.6 to 12 4.1 to 5.7 i l v in v out ? l ----------------------------- - t on ? v out v f + l --------------------------- - t off ? == l min v out v f + i max --------------------------- - 1d min ? f sw ---------------------- - ? = i lpk , i o i l 2 -------- + = application informations l7980 18/44 doc id 15181 rev 4 6.3 output capacitor selection the current in the capacitor has a triangular waveform which generates a voltage ripple across it. this ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its esr). so the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. the amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. equation 12 usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (mlcc) with very low esr value. the output capacit or is important also for lo op stability: it fixes the double lc filter pole and the zero due to its esr. in chapter 6.4 , it will be illustrated how to consider its effect in the system stability. for example with v out =5 v, v in =24 v, i l =0.6 a (resulting by the indu ctor value), in order to have a v out =0.01v out , if the multi layer ceramic capacitor are adopted, 10 f are needed and the esr effect on the output voltage ripple can be neglected. in case of not negligible esr (electrolytic or tantalum capacitors), th e capacitor is chosen taking into account its esr value. so in case of 220 with esr=50 m , the resistive component of the drop dominates and the voltage ripple is 33 mv . the output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. when the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. so if the high slew rate load transient is required by the application the output capacitor and system bandwidth have to be chosen in order to sustain the load transient. in the table below some capacitor series are listed. table 8. output capacitors manufacturer series cap value ( f) rated voltage (v) esr (m ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 v out esr i max ? i max 8c out f sw ?? ------------------------------------ - + = l7980 application informations doc id 15181 rev 4 19/44 6.4 compensation network the compensation network has to assure stab ility and good dynamic performance. the loop of the l7980 is based on the voltage mode control. the error amplifier is a voltage operational amplifier with high bandwidth. so selecting the compensation network the e/a will be considered as ideal, that is, its bandwidth is much larger than the system one. the transfer functions of pwm modulator and the output lc filter are studied (see figure 10. ). the transfer function of the pwm modulator, from the error amplifier output (comp pin) to the out pin, results: equation 13 where v s is the sawtooth amplitude. as seen in chapter 5.1 , the voltage feed forward generates a sawtooth amplitude directly proportional to the input voltage, that is: equation 14 in this way the pwm modulator gain results constant and equals to: equation 15 the synchronization of the device with an external clock provided trough synch pin can modifies the pwm modulator gain (see chapter 5.1 to understand how this gain changes and how to keep it constant in spite of the external synchronization). figure 9. the error amplifier, the pwm modulation and the lc output filter the transfer function on the lc filter is given by: g pw0 v in v s -------- - = v s kv in ? = g pw0 v in v s -------- - 1 k --- - 13 === fb comp v ref e/a pwm v s out v cc c out esr l g pw0 g lc fb comp v ref e/a pwm v s out v cc c out esr l g pw0 g lc application informations l7980 20/44 doc id 15181 rev 4 equation 16 where: equation 17 equation 18 as seen in chapter 5.3 two different kind of network can compensate the loop. in the two following paragraph the guidelines to select the type ii and type iii compensation network are illustrated. 6.4.1 type iii compensation network the methodology to stabilize the loop consists of placing two zeros to compensate the effect of the lc double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero db frequency. if the equivalent series resistance (esr) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 ? esr ? cout<1/bw), the type iii compensation network is needed. multi layer ceramic capacitors (mlcc) have very low esr (<1m ), with very high frequency zero, so type iii network is adopted to compensate the loop. in figure 10 the type iii compensation network is shown. this network introduces two zeros (f z1 , f z2 ) and three poles (f p0 , f p1 , f p2 ). they expression are: equation 19 g lc s () 1 s 2 f zesr ? ------------------------- - + 1 s 2 qf ? lc ? ---------------------------- s 2 f lc ? ------------------- ?? ?? 2 ++ ------------------------------------------------------------------------- = f lc 1 2 lc out ? 1 esr r out -------------- - + ?? ----------------------------------------------------------------------- - = f zesr 1 2 esr c out ?? ------------------------------------------- - = , q r out lc out r out esr + () ?? ? lc out r out esr ?? + ------------------------------------------------------------------------------------------ r out v out i out -------------- = , = f z1 1 2 c 3 r 1 r 3 + () ?? ------------------------------------------------ = f z2 1 2 r 4 c 4 ?? ----------------------------- - = , l7980 application informations doc id 15181 rev 4 21/44 equation 20 figure 10. type iii compensation network in figure 11 the bode diagram of the pwm and lc filter transfer function (g pw0 g lc (f)) and the open loop gain (g loop (f) = g pw0 g lc (f) g typeiii (f)) are drawn. figure 11. open loop gain: module bode diagram the guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. choose a value for r 1 , usually between 1 k and 5 k . 2. choose a gain (r 4 /r 1 ) in order to have the required bandwidth (bw), that means: f p0 0 = f p1 1 2 r 3 c 3 ?? ----------------------------- - = f p2 1 2 r 4 c 4 c 5 ? c 4 c 5 + -------------------- ?? ------------------------------------------- - = ,, application informations l7980 22/44 doc id 15181 rev 4 equation 21 where k is the feed forward constant and 1/k is equals to 9. 3. calculate c 4 by placing the zero at 50% of the output filter double pole frequency (f lc ): equation 22 4. calculate c 5 by placing the second pole at four times the system bandwidth (bw): equation 23 5. set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole: equation 24 the suggested maximum system ba ndwidth is equals to the sw itching frequency divided by 3.5 (f sw /3.5), anyway lower than 100 khz if the f sw is set higher than 500 khz. for example with v out =5 v, v in =24 v, i o =2 a, l=27 h, c out =22 f, esr<1 m , the type iii compensation network is: in figure 12 is shown the module and phase of the open loop gain. the bandwidth is about 54 khz and the phase margin is 50. r 4 bw f lc --------- - kr 1 ?? = c 4 1 r 4 f lc ?? --------------------------- = c 5 c 4 2 r 4 c 4 4bw ? 1 ? ??? ------------------------------------------------------------- - = r 3 r 1 4bw ? f lc ----------------- 1 ? -------------------------- - = c 3 1 2 r 3 4bw ??? ---------------------------------------- - = , r 1 4.99k = r 2 680 = r 3 150 = r 4 3.3k = c 3 4.7nf = c 4 22nf = c 5 220pf = ,,,, ,, l7980 application informations doc id 15181 rev 4 23/44 figure 12. open loop gain bode di agram with ceramic output capacitor application informations l7980 24/44 doc id 15181 rev 4 6.4.2 type ii com pensation network if the equivalent series resistance (esr) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2 ? esr ? cout>1/bw), this zero helps stabilize the loop. electrolytic capaci tors show not negligible esr (>30 m ), so with this kind of output capacitor the type ii network combined with the zero of the esr allows stabilizing the loop. in figure 13 the type ii network is shown. figure 13. type ii compensation network the singularities of the network are: in figure 14 the bode diagram of the pwm and lc filter transfer function (g pw0 g lc (f)) and the open loop gain (g loop (f) = g pw0 g lc (f) g typeii (f)) are drawn. f z1 1 2 r 4 c 4 ?? ----------------------------- - = f p0 0 = f p1 1 2 r 4 c 4 c 5 ? c 4 c 5 + -------------------- ?? ------------------------------------------- - = ,, l7980 application informations doc id 15181 rev 4 25/44 figure 14. open loop gain: module bode diagram the guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. choose a value for r 1 , usually between 1 k and 5 k , in order to have values of c4 and c5 not comparable with parasitic capacitance of the board. 2. choose a gain (r 4 /r 1 ) in order to have the required bandwidth (bw), that means: equation 25 where f esr is the esr zero: equation 26 and vs is the saw-tooth amplitude. the voltage feed forward keeps the ratio vs/vin constant. 3. calculate c 4 by placing the zero one decade below the output filter double pole: equation 27 4. then calculate c 3 in order to place the second pole at four times the system bandwidth (bw): r 4 f esr f lc ----------- - ?? ?? 2 bw f esr ----------- - v s v in -------- - r 1 ??? = f esr 1 2 esr c out ?? ------------------------------------------- - = c 4 10 2 r 4 f lc ?? ------------------------------ - = application informations l7980 26/44 doc id 15181 rev 4 equation 28 for example with v out =5 v, v in =24 v, i o =2 a, l=27 h, c out =330 f, esr=50 m , the type ii compensation network is: in figure 15 is shown the module and phase of the open loop gain. the bandwidth is about 24 khz and the phase margin is 48. c 5 c 4 2 r 4 c 4 4bw ? 1 ? ??? ------------------------------------------------------------- - = r 1 1.1k = r 2 150 = r 4 6.8k = c 4 82nf = c 5 82pf = ,, ,, l7980 application informations doc id 15181 rev 4 27/44 figure 15. open loop gain bode diagram wi th electrolytic/tantalum output capacitor application informations l7980 28/44 doc id 15181 rev 4 6.5 thermal considerations the thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 c. the three different sources of losses within the device are: a) conduction losses due to the not negligible r dson of the power switch; these are equal to: equation 29 where d is the duty cycle of the application and the maximum r dson over temperature is 300 m . note that the duty cycle is theoretically given by the ratio between v out and v in , but actually it is quite higher to compensate the losses of the regulator. so the conduction losses increases compar ed with the ideal case. b) switching losses due to power mosfet turn on and off; these can be calculated as: equation 30 where t rise and t fall are the overlap times of the voltage across the power switch (v ds ) and the current flowing into it during turn on and turn off phases, as shown in figure 16 . t sw is the equivalent switching time. for this device the typical value for the equivalent switching time is 30 ns. c) quiescent current losses, calculated as: equation 31 where i q is the quiescent current (i q =2.4 ma). the junction temperature t j can be calculated as: equation 32 where t a is the ambient temperature and p tot is the sum of the power losses just seen. r thja is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. for this device the path through the exposed pad is the one conducting the largest amount p on r dson i out () 2 d ?? = p sw v in i out t rise t fall + () 2 ------------------------------------------ - fsw ?? ? v in i out t sw f sw ??? == p q v in i q ? = t j t a rth ja p tot ? + = l7980 application informations doc id 15181 rev 4 29/44 of heat. the rth ja measured on the demonstration board described in the following paragraph is about 60 c/w for the vfqfpn package and about 40 c/w for the hsop package. figure 16. switching losses 6.6 layout considerations the pc board layout of switching dc/dc regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. in a step down converter the input loop (including the input capacitor, the power mosfet and the free wheeling diode) is the most critical one. this is due to the fact that the high value pulsed current are flowing through it. in order to minimize the emi, this loop has to be as short as possible. the feedback pin (fb) connection to external re sistor divider is a high impedance node, so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. to reduce the pick up noise the resistor divider has to be placed very close to the device. to filter the high frequency noise, a small bypass capacitor (220 nf - 1 f) can be added as close as possible to the input voltage pin of the device. thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion. in figure 17 a layout example is shown. application informations l7980 30/44 doc id 15181 rev 4 figure 17. layout example l7980 application informations doc id 15181 rev 4 31/44 6.7 application circuit in figure 18 the demonstration board application circuit is shown. figure 18. demonstration board application circuit (rev 1.0) table 9. component list (rev 1.0) reference part number description manufacturer c1 umk325bj106mm-t 10 f, 50v taiyo yuden c2 grm32er61e226ke15 22 f, 25v murata c3 2.2nf, 50v c4 22nf, 50v c5 220pf, 50v c6 470nf, 50v r1 4.99k , 1%, 0.1w 0603 r2 1.1k , 1%, 0.1w 0603 r3 220 , 1%, 0.1w 0603 r4 2.2k , 1%, 0.1w 0603 r5 100k , 1%, 0.1w 0603 d1 stps3l40 3a dc, 40v stmicroelectronics l1 mss1038-103nl 10 h, 30%, 3.9a, dcr max =35m coilcraft application informations l7980 32/44 doc id 15181 rev 4 figure 19. pcb layout: l7980 and l7980a (component side) figure 20. pcb layout: l7980 and l7980a (bottom side) figure 21. pcb layout: l7980 and l7980a (front side) l7980 application informations doc id 15181 rev 4 33/44 figure 22. junction temperature vs. output current figure 23. junction temperature vs. output current figure 24. junction temperature vs. output current figure 25. efficiency vs. output current figure 26. efficiency vs.output current figure 27. efficiency vs. output current 72 77 82 87 92 0.0 0.5 1.0 1.5 2.0 io [a] eff [%] v out =5.0 v fsw=250 khz v in =18v v in =12v v in =24v 65 70 75 80 85 90 95 0.0 0.5 1.0 1.5 2.0 io [a] eff [%] v out =3.3 v fsw=250 khz v in =5v v in =12v v in =24v 50 55 60 65 70 75 80 85 0.00.51.01.52.0 io [a] eff [%] v out =1.8 v fsw=250 khz v in =5v v in =12v v in =24v application informations l7980 34/44 doc id 15181 rev 4 figure 28. load regulation figure 29. line regulation figure 30. load transient: from 0.4 a to 2 a figure 31. soft start figure 32. short circuit behavior 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.5 1 1.5 2 io [a] v fb /v fb [%] vcc=5v vcc=12v vcc=24v -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 510152025 v cc [v] v fb /v fb [%] io=1a io=2a v out 100mv/div ac coupled i l 500ma/div time base 100us/div v in =24v v out =3.3v c out =47uf l=10uh f sw =520k v out 100mv/div ac coupled i l 500ma/div time base 100us/div v in =24v v out =3.3v c out =47uf l=10uh f sw =520k v out 500mv/div v fb 200mv/div i l 500ma/div time base 1ms/div v out 500mv/div v fb 200mv/div i l 500ma/div time base 1ms/div i l 500ma/div v out 1v/div out 10v/div output shorted time base 5ms/div i l 500ma/div v out 1v/div out 10v/div output shorted time base 5ms/div l7980 application ideas doc id 15181 rev 4 35/44 7 application ideas 7.1 positive buck-boost the l7980 can implement the step up/down converter with a positive output voltage. figure 33. shows the schematic: one power mosfet and one schottky diode are added to the standard buck topology to provide 12 v output voltage with input voltage from 4.5 v to 28 v. figure 33. positive buck-boost regulator the relationship between input and output voltage is: equation 33 so the duty cycle is: equation 34 the output voltage isn?t limited by the maximum operating voltage of the device (28 v), because the output voltage is sense only through the resistor divider. the external power mosfet maximum drain to source voltage, must be higher than output voltage; the maximum gate to source voltage must be higher than the input voltage (in figure 33. , if v in is higher than 16 v, the gate must be protected through zener diode and resistor) the current flowing through the internal power mosfet is transferred to the load only during the off time, so according to the maximum dc switch current (2.0 a), the maximum output current for the buck boost topology can be calculated from the following equation. v out v in d 1d ? ------------- ? = d v out v out v in + ----------------------------- - = application ideas l7980 36/44 doc id 15181 rev 4 equation 35 where i sw is the average current in the embedded power mosfet in the on time. to chose the right value of the inductor and to manage transient output current, that for short time can exceed the maximum output current calculated by equation 35 , also the peak current in the power mosfet has to be calculated. the peak current, showed in equation 36 , must be lower than the minimum current limit (3.7 a) equation 36 where r is defined as the ratio between the inductor current ripple and the inductor dc current: so in the buck boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value). in figure 34. the maximum output current for the above configuration is depicted varying the input voltage from 4.5 v to 28 v. the dashed line considers a more accurate estimation of the duty cycles given by equation 37 , where power losses across diodes, external power mosfet, internal power mosfet are taken into account. i sw i out 1d ? ------------- 2 a < = i sw,pk i out 1d ? ------------- 1 r 2 -- - + 2.5a < ? = r v out i out lf sw ?? ------------------------------------ 1d ? () 2 ? = l7980 application ideas doc id 15181 rev 4 37/44 figure 34. maximum output current according to max dc switch current (2.0 a): v o =12 v equation 37 where v d is the voltage drop across diodes, v sw and v swe across the internal and external power mosfet. 7.2 inverting buck-boost the l7980 can implement the step up/down converter with a negative output voltage. figure 33. shows the schematic to regulate -5 v: no further external components are added to the standard buck topology. the relationship between input and output voltage is: equation 38 so the duty cycle is: equation 39 d v out 2v d ? + v in v sw v swe v out 2v ? d ++ ? ? ------------------------------------------------------------------------------------------- - = v out v in ? d 1d ? ------------- ? = d v out v out v in ? ----------------------------- - = application ideas l7980 38/44 doc id 15181 rev 4 as in the positive one, in the inverting buck-boost the current flowing through the power mosfet is transferred to the load only during the off time. so according to the maximum dc switch current (2.0 a), the maximum output current can be calculated from the equation 35 , where the duty cycle is given by equation 39 . figure 35. inverting buck-boost regulator the gnd pin of the device is connected to the output voltage so, given the output voltage, input voltage range is limited by the maximum voltage the device can withstand across vcc and gnd (28 v). thus if the output is -5 v the input voltage can range from 4.5 v to 23 v. as in the positive buck-boost, the maximum output current according to application conditions is shown in figure 36 . the dashed line considers a more accurate estimation of the duty cycles given by equation 40 , where power losses across diodes and internal power mosfet are taken into account. equation 40 figure 36. maximum output current according to max dc switch current (2.0 a): v o =-5 v d v out v d ? v ? in v sw v out v d ? + ? ---------------------------------------------------------------- - = l7980 package mechanical data doc id 15181 rev 4 39/44 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. package mechanical data l7980 40/44 doc id 15181 rev 4 figure 37. package dimensions table 10. vfqfpn8 (3x3x1.08mm) mechanical data dim. mm inch min typ max min typ max a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.02 0.05 0.0008 0.0020 a2 0.70 0.0276 a3 0.20 0.0079 b 0.18 0.23 0.30 0.0071 0.0091 0.0118 d 2.95 3.00 3.05 0.1161 0.1181 0.1200 d2 2.23 2.38 2.48 0.0878 0.0937 0.0976 e 2.95 3.00 3.05 0.1161 0.1181 0.1200 e2 1.65 1.70 1.75 0.0649 0.0669 0.0689 e 0.50 0.0197 l 0.35 0.40 0.45 0.0137 0.0157 0.0177 ddd 0.08 0.0031 l7980 package mechanical data doc id 15181 rev 4 41/44 table 11. hsop8 mechanical data figure 38. package dimensions dim mm inch min typ max min typ max a 1.70 0.0669 a1 0.00 0.15 0.00 0.0059 a2 1.25 0.0492 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 d 4.80 4.90 5.00 0.1890 0.1929 0.1969 e 5.80 6.00 6.20 0.2283 0.2441 e1 3.80 3.90 4.00 0.1496 0.1575 e1.27 h 0.25 0.50 0.0098 0.0197 l 0.40 1.27 0.0157 0.0500 k0 8 0.3150 ccc 0.10 0.0039 order codes l7980 42/44 doc id 15181 rev 4 9 order codes table 12. order codes order codes package packaging l7980 vfqfpn8 tube l7980a hsop8 tube L7980TR vfqfpn8 tape and reel l7980atr hsop8 tape and reel l7980 revision history doc id 15181 rev 4 43/44 10 revision history table 13. document revision history date revision changes 19-nov-2008 1 initial release. 12-mar-2009 2 content reworked to improve readability, no technical changes 01-jul-2010 3 added application information 13-dec-2010 4 updated: section 6.5 on page 28 l7980 44/44 doc id 15181 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 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